Hermetic wafer-to-wafer bonding with electrical interconnection

ABSTRACT

An implantable medical device (IMD) is disclosed. The IMD includes a first substrate having a front side and a backside. A first via is formed in the front side, the via extending from a bottom point in the front side to a first height located at a surface of the front side. A first conductive pad is formed in the first via, the first conductive pad having an exposed top surface lower than first height. A second substrate is coupled to the first substrate, the second substrate having a second via formed in the front side, the via extending from a bottom point in the front side to a second height located at a surface of the front side. A second conductive pad is formed in the second via, the second conductive pad having an exposed top surface lower than second height. The coupled substrates are heated until a portion of one or both conductive pads reflow, dewet, agglomerate, and merge to form an interconnect, hermetic seal, or both depending on the requirements of the device.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to creating electrical interconnections between materials, and, more particularly, to creating electrical interconnections between materials that are compatible with low temperature hermetic wafer-to-wafer bonds. Additionally, the methods described herein can be applied to creating hermetic metal seals between wafers.

BACKGROUND

Many electronic components use integrated circuits or chips. An IC is comprised of semiconductor devices (e.g. diode, transistor etc.) and passive components (e.g., transistors, capacitors, resistors, etc.) that are formed in the surface of a thin substrate of semiconductor material.

One IC can be connected to another IC or other wafer through wafer to wafer bonds. Wafer to wafer bonds relates to joining major surfaces of the wafers. The joined areas of the wafers creates the hermetic seal(s).

One type of wafer to wafer bond relies on a copper pad disposed on each wafer. The copper pad is higher than the surrounding plane of the wafer. A copper pad on one wafer is aligned with the copper pad on the other wafer. Thermo-compression diffusion bonding can be employed to join the copper pads located on each wafer. The ICs are then sealed together with a copper seal ring or a race track near the outer edges of the individual chips. Copper is not biostable and may not provide an adequate seal in vivo for implantable medical devices. Additionally, copper pads that are coplanar with a thermal oxide can be difficult to planarize and polish. For example, copper and thermal oxide can have different polishing rates. It is therefore desirable to develop new techniques for efficiently and hermetically sealing the electronic circuitry in IMDs.

SUMMARY

The present disclosure relates to an implantable medical device (IMD) that includes one or more integrated circuits. At least one integrated circuit includes a first substrate bonded to a second substrate. The first substrate has a front side and a backside. A first via is formed in the front side. The via extends from a bottom point to a first height located at a surface of the front side. A first conductive pad is formed in the first via. The first conductive pad has a bottom surface and a top surface. The first conductive pad has an exposed top surface lower than the first height of the via. In one or more embodiments, the second substrate has a second via formed in the front side. The via extends from a bottom point to a second height located at a surface of the front side. A second conductive pad is formed in the second via. The second conductive pad has an exposed top surface lower than second height. Heat is applied to the first and second substrates, which in response causes the first and second conductive pads to flow and form a single reflowed interconnect between the first and second substrates.

In one or more other embodiments, a method is disclosed for forming an integrated circuit for an implantable medical device. In one or more embodiments, a first via is formed in a first side of a first substrate. A first conductive pad is then deposited in the first via. An exposed top surface of the first conductive pad is lower than a top surface of the first via. In one or more embodiments, a second via is formed in a first side of a second substrate. A second conductive pad is deposited in the second via. An exposed top surface of the second conductive pad is lower than a top surface of the second via. Heat is applied which causes the portions of the first and second conductive pads to dewet. For example, portions of the first and second conductive pads can dewet in areas in which the pads are deposited on an insulator such as glass, (also referred to as thermal oxide (i.e. SiO₂). In response to having a first and second conductive pad that have an exposed surface below the height of each corresponding via and to the heat, a conductive agglomeration or a single reflowed interconnect forms between and joins together first and second conductive pads The join together. The conductive interconnect formed between the first and second substrates can be dome shaped, hour glass shaped, or spherically shaped. The conductive interconnect creates a mechanical and electrical interconnect between the first and second substrates. Multiple interconnects can be formed in this manner between the first and second substrates. When cooled, the resultant interconnected device can be produced.

In one or more other embodiments, a racetrack can be formed around the periphery of the device in the same fashion as described between first and second conductive pads disposed in the first and second substrates. After heating and cooling, a hermetic seal is formed along the racetrack. The hermetic seal formed along the racetrack eliminates the need for additional packaging that is typically found in conventional devices due to the hermetic seal formed by the racetrack. The lack of additional packaging allows the device to be significantly reduced in size compared to conventional devices.

In one or more embodiments, the first and/or second substrates are formed from biostable wafers such as glass or silicon. For example, the first substrate bonded to the second substrate can be glass-glass, glass-silicon, or silicon-silicon bonding are formed across an entire wafer with the exception of small recessed areas containing the pad structures and racetrack or seal as it will be known hereafter.

In one or more embodiments, the first and/or second conductive pads are supported by an underlying adhesion or barrier material. Adhesion material can comprise transition metal elements such as chromium and/or titanium along with a wettable material such as gold. The first conductive pad such as gold tin (AuSn) is deposited in a thin layer over the wettable pad and the area of the AuSn deposit is larger than the wettable pad. The top of the AuSn metallization remains below the upper surface of the wafer so as not to interfere with the wafer bonding. After or during wafer bonding, the temperature is raised above the melting point of the AuSn (˜280 C). The AuSn dewets from the glass surrounding the gold pad and can form a substantially spherical or dome shape on the pad. The height of this solder bump or ball is determined by the size of the pad and the area and volume of AuSn deposited over the pad and surrounding glass. During melting, the top of the AuSn ball joins to a similar AuSn ball, or to a wettable pad on the mating wafer. The same or similar process can be used to create a seal around the periphery of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram illustrating an exemplary therapy system including an implantable cardiac device (ICD).

FIG. 2 is a conceptual diagram illustrating the ICD of FIG. 1 and the respective leads in greater detail.

FIG. 3 is a conceptual diagram illustrating the ICD of FIGS. 1 and 2 and the respective leads in greater detail.

FIG. 4 is a functional block diagram of an example ICD that generates and delivers electrical stimulation to a heart of a patient.

FIG. 5 is a functional block diagram of an example medical device programmer.

FIG. 6 depicts a schematic view of a substrate that has undergone a grinding operation.

FIG. 7 depicts a schematic side view of the substrate of FIG. 6 that has undergone a cleaning operation.

FIG. 8 depicts a schematic side view of a thermal oxide formed on the front and backsides of the substrate shown in FIG. 7.

FIG. 9 depicts a schematic side view of a backside of the substrate of FIG. 8 in which a scribe is formed in the backside.

FIG. 10 depicts a schematic side view of the substrate of FIG. 9 in which thermal oxide is removed therefrom.

FIG. 11 depicts a schematic side view of the substrate of FIG. 10 that has undergone a cleaning operation.

FIG. 12 depicts a schematic side view of thermal oxide formed over the substrate shown in FIG. 11.

FIG. 13 depicts a schematic side view of photoresist deposited over the thermal oxide shown in FIG. 12.

FIG. 14 depicts a schematic side view of a mask placed over the photoresist shown in FIG. 13.

FIG. 15 depicts a schematic side view of exposed photoresist removed from a thermal oxide layer shown in FIG. 14.

FIG. 16 depicts a schematic side view of an exposed thermal oxide removed from FIG. 15.

FIG. 17 depicts removal of a remaining portion of photoresist as compared to the substrate depicted in FIG. 16.

FIG. 18 depicts a schematic view of the substrate of in FIG. 17 undergoing a cleaning operation.

FIG. 19 depicts a schematic view of thermal oxide formed over the substrate of FIG. 18.

FIG. 20 depicts a schematic view of photoresist being applied to the backside of the substrate shown in FIG. 19.

FIG. 21 depicts a schematic view of a mask placed over the photoresist shown in FIG. 20.

FIG. 22 depicts a schematic view of exposed photoresist removed from the substrate shown in FIG. 21.

FIG. 23 depicts a schematic view of vias formed in the thermal oxide of the substrate shown in FIG. 22.

FIG. 24 depicts a schematic view of photoresist being removed from the thermal oxide on the substrate shown in FIG. 23.

FIG. 25 depicts a schematic view of a pad formed of first, second and third conductive materials deposited in a via located in thermal oxide on a frontside of the substrate shown in FIG. 24.

FIG. 26 depicts a schematic view of photoresist deposited over the third conductive material shown in FIG. 25.

FIG. 27 depicts a schematic view of a mask placed over a portion of the photoresist shown in FIG. 26.

FIG. 28 depicts a schematic view of exposed photoresist removed from the third conductive metal shown in FIG. 27.

FIG. 29 depicts a schematic view of a portion of the first, second and third conductive materials being removed.

FIG. 30 depicts a schematic view of the remaining portion of the photoresist being removed.

FIG. 31 depicts a schematic view of an insulative layer over the first, second and third conductive materials.

FIG. 32 depicts a schematic view of photoresist formed over the insulative layer shown in FIG. 31.

FIG. 33 depicts a schematic view of a mask over the photoresist as shown in FIG. 32.

FIG. 34 depicts a schematic view of a portion of the photoresist removed from the substrate shown in FIG. 33.

FIG. 35 depicts a schematic view of a portion of the insulative layer is etched from the third conductive material as shown in FIG. 34.

FIG. 36 depicts a schematic view of the removal of the remaining photoresist from the insulative layer.

FIG. 37 depicts a schematic view of a portion of the third conductive material removed from the second conductive material.

FIG. 38 depicts a schematic view of gold tin deposited over the second conductive material and the insulative layer.

FIG. 39 depicts a schematic view of photoresist formed over the gold tin shown in FIG. 38.

FIG. 40 depicts a schematic view of a mask over the photoresist shown in FIG. 39.

FIG. 41 depicts a schematic view of exposed photoresist being removed from the component shown in FIG. 40.

FIG. 42 depicts a schematic view of a portion of the gold tin being etched from the thermal oxide layer shown in FIG. 41.

FIG. 43 depicts a schematic view of a portion of the photoresist being removed from the gold tin layer shown in FIG. 42.

FIG. 44 depicts a schematic view of a top surface of the insulative layer being polished.

FIG. 44 a depicts a schematic view of a finished wafer in which conductive material has undergone a reflow process.

FIG. 45 depicts a schematic view of a frontside of a first substrate coupled to a frontside of a second substrate.

FIG. 46 depicts a schematic view of a hermetic bond between the first and second substrates.

FIG. 47 depicts a schematic view of the gold tin extending between the first and second substrates to form an interconnect.

FIG. 48 depicts a schematic view of vias formed through a substrate.

FIG. 49 depicts a schematic view of thermal oxide being removed from one of the substrates shown in FIG. 48.

FIG. 50 depicts a flow diagram of a method for forming pads capable of forming interconnects between wafers that will undergo a wafer to wafer bond.

FIG. 51 depicts a schematic side view of a wafer to wafer bond with an oxide overlap.

FIG. 52 depicts a schematic side view of a wafer to wafer bond without an oxide overlap.

FIG. 53 depicts a schematic view of a bump to pad structure before a reflow process.

FIG. 54 depicts a schematic view of the bump to pad structure shown in FIG. 53 after a reflow process.

FIG. 55 depicts a schematic view after a substrate has undergone a cleaning operation and formation of thermal oxide over a first and a second side of the substrate.

FIG. 56 depicts a schematic view of formation of a first pad layer over a side of the substrate.

FIG. 57 depicts a schematic view in which a thin layer thermal oxide is formed over the entire surface of the substrate.

FIG. 58 depicts a schematic view of conductive metals formed in a via.

FIG. 59 depicts a schematic view of a portion of the first, second and third conductive materials being removed.

FIG. 60 depicts a schematic view of gold tin deposited over a conductive material.

FIG. 61 depicts a schematic view in which a portion of the conductive metal is removed.

FIG. 62 depicts the thermal oxide layer after undergoing a touch polish operation.

FIG. 63 depicts a bump to bump structure formed by the processes depicted in FIGS. 55-62.

FIG. 64 depicts a schematic view of a bump to mating metal pad structure after a reflow process.

FIG. 65 depicts a schematic view of the bump to pad structure shown in before a reflow process.

FIG. 66 depicts a schematic view of the bump to pad structure shown in after a reflow process.

FIG. 67 depicts thermal oxide formed over two sides of a substrate.

FIG. 68 depicts formation of a via in thermal oxide on one side of the substrate depicted in FIG. 67.

FIG. 69 depicts a thin layer of thermal oxide formed on the entire surface of a substrate shown in FIG. 68.

FIG. 70 depicts a schematic view of conductive material deposited into the via shown in FIG. 69.

FIG. 71 depicts a portion of the first, second and third conductive materials removed.

FIG. 72 depicts chemical vapor deposition of oxide or nitride or both over the conductive material.

FIG. 73 depicts a portion of the oxide or nitride layer removed from the structure shown in FIG. 72.

FIG. 74 depicts a portion of the conductive layer removed from the structure shown in FIG. 73.

FIG. 75 depicts gold tin deposited over the structure depicted in FIG. 74.

FIG. 76 depicts a portion of the gold tin removed from the structure depicted in FIG. 75.

FIG. 77 depicts the structure of FIG. 76 after it has undergone a light polishing operation.

FIG. 78 depicts a frontside of one wafer coupled to the frontside of another wafer.

FIG. 79 depicts a wafer to wafer bond formed from the embodiment shown in FIG. 78.

FIG. 80 depicts another embodiment in which one of the wafers includes a mating metal pad.

FIG. 81 depicts a bump and mating metal pad after reflow.

FIG. 82 depicts a top view of a seal ring in which the wafer to wafer interconnect technology is implemented to form a hermetic seal.

FIG. 83 depicts a schematic view of a bump structure with the significant geometries labeled.

FIG. 84 depicts SEMs of a reflowed, dome shaped, single bump without a mating bump.

DETAILED DESCRIPTION

The present disclosure depicted in FIGS. 6-84 and the accompanying text discloses formation of a wafer to wafer bond and electrical connections that can be used in a variety of implantable medical devices (IMDs) shown in FIGS. 1-5 in which small size, hermeticity and multiple die connection is desired. A variety of components can employ the technology described herein. Sensors (e.g. wireless sensors, leaded sensors), smart leads and/or miniature therapeutic devices exemplify the type of components that can implement the teachings of the present disclosure. The sensor, smart lead or miniature devices may or may not be protected and enclosed in an implantable cardioverter defibrillator (ICD) titanium can or housing.

It will be apparent that elements from one embodiment may be used in combination with elements of the other embodiments, and that the possible embodiments of such apparatus using combinations of features set forth herein is not limited to the specific embodiments shown in the Figures and/or described herein. Further, it will be recognized that the embodiments described herein may include many elements that are not necessarily shown to scale. Further, it will be recognized that the size and shape of various elements herein may be modified but still fall within the scope of the present disclosure, although one or more shapes and/or sizes, or types of elements, may be advantageous over others.

FIG. 1 is a conceptual diagram illustrating an example therapy system 10 that may be used to provide therapy to heart 12 of patient 14. Therapy system 10 includes one or more integrated circuits that incorporate the semiconductor processing described herein. Patient 12 ordinarily, but not necessarily, will be a human. Therapy system 10 includes IMD 16, which is coupled to leads 18, 20, and 22, and programmer 24. IMD 16 may be, for example, an implantable pacemaker, cardioverter, and/or defibrillator that provides electrical signals to heart 12 via electrodes coupled to one or more of leads 18, 20, and 22.

Leads 18, 20, 22 extend into the heart 12 of patient 16 to sense electrical activity of heart 12 and/or deliver electrical stimulation to heart 12. In the example shown in FIG. 1, right ventricular (RV) lead 18 extends through one or more veins (not shown), the superior vena cava (not shown), and right atrium 26, and into right ventricle 28. Left ventricular (LV) coronary sinus lead 20 extends through one or more veins, the vena cava, right atrium 26, and into the coronary sinus 30 to a region adjacent to the free wall of left ventricle 32 of heart 12. Right atrial (RA) lead 22 extends through one or more veins and the vena cava, and into the right atrium 26 of heart 12.

IMD 16 may sense electrical signals attendant to the depolarization and repolarization of heart 12 via electrodes (not shown in FIG. 1) coupled to at least one of the leads 18, 20, 22. In some examples, IMD 16 provides pacing pulses to heart 12 based on the electrical signals sensed within heart 12. The configurations of electrodes used by IMD 16 for sensing and pacing may be unipolar or bipolar. IMD 16 may also provide defibrillation therapy and/or cardioversion therapy via electrodes located on at least one of the leads 18, 20, 22. IMD 16 may detect arrhythmia of heart 12, such as fibrillation of ventricles 28 and 32, and deliver defibrillation therapy to heart 12 in the form of electrical pulses. In some examples, IMD 16 may be programmed to deliver a progression of therapies, e.g., pulses with increasing energy levels, until a fibrillation of heart 12 is stopped. IMD 16 detects fibrillation employing one or more fibrillation detection techniques known in the art.

In some examples, programmer 24 may be a handheld computing device or a computer workstation. Programmer 24 may include a user interface that receives input from a user. The user interface may include, for example, a keypad and a display, which may for example, be a cathode ray tube (CRT) display, a liquid crystal display (LCD) or light emitting diode (LED) display. The keypad may take the form of an alphanumeric keypad or a reduced set of keys associated with particular functions. Programmer 24 can additionally or alternatively include a peripheral pointing device, such as a mouse, via which a user may interact with the user interface. In some embodiments, a display of programmer 24 may include a touch screen display, and a user may interact with programmer 24 via the display.

A user, such as a physician, technician, or other clinician, may interact with programmer 24 to communicate with IMD 16. For example, the user may interact with programmer 24 to retrieve physiological or diagnostic information from IMD 16. A user may also interact with programmer 24 to program IMD 16, e.g., select values for operational parameters of the IMD.

For example, the user may use programmer 24 to retrieve information from IMD 16 regarding the rhythm of heart 12, trends therein over time, or tachyarrhythmia episodes. As another example, the user may use programmer 24 to retrieve information from IMD 16 regarding other sensed physiological parameters of patient 14, such as intracardiac or intravascular pressure, activity, posture, respiration, or thoracic impedance. As another example, the user may use programmer 24 to retrieve information from IMD 16 regarding the performance or integrity of IMD 16 or other components of system 10, such as leads 18, 20, and 22, or a power source of IMD 16.

The user may use programmer 24 to program a therapy progression, select electrodes used to deliver defibrillation shocks, select waveforms for the defibrillation shock, or select or configure a fibrillation detection algorithm for IMD 16. The user may also use programmer 24 to program aspects of other therapies provided by IMD 14, such as cardioversion or pacing therapies. In some examples, the user may activate certain features of IMD 16 by entering a single command via programmer 24, such as depression of a single key or combination of keys of a keypad or a single point-and-select action with a pointing device.

IMD 16 and programmer 24 may communicate via wireless communication using any techniques known in the art. Examples of communication techniques may include, for example, low frequency or radiofrequency (RF) telemetry, but other techniques are also contemplated. In some examples, programmer 24 may include a programming head that may be placed proximate to the patient's body near the IMD 16 implant site in order to improve the quality or security of communication between IMD 16 and programmer 24.

FIG. 2 is a conceptual diagram illustrating IMD 16 and leads 18, 20, 22 of therapy system 10 in greater detail. Leads 18, 20, 22 may be electrically coupled to a stimulation generator, a sensing module, or other modules IMD 16 via connector block 34. In some examples, proximal ends of leads 18, 20, 22 may include electrical contacts that electrically couple to respective electrical contacts within connector block 34. In addition, in some examples, leads 18, 20, 22 may be mechanically coupled to connector block 34 with the aid of set screws, connection pins or another suitable mechanical coupling mechanism.

Each of the leads 18, 20, 22 includes an elongated insulative lead body, which may carry a number of concentric coiled conductors separated from one another by tubular insulative sheaths. In the illustrated example, a pressure sensor 38 and bipolar electrodes 40 and 42 are located proximate to a distal end of lead 18. In addition, bipolar electrodes 44 and 46 are located proximate to a distal end of lead 20 and bipolar electrodes 48 and 50 are located proximate to a distal end of lead 22. In FIG. 2, pressure sensor 38 is disposed in right ventricle 28. Pressure sensor 38 may respond to an absolute pressure inside right ventricle 28, and may be, for example, a capacitive or piezoelectric absolute pressure sensor. In other examples, pressure sensor 38 may be positioned within other regions of heart 12 and may monitor pressure within one or more of the other regions of heart 12, or may be positioned elsewhere within or proximate to the cardiovascular system of patient 14 to monitor cardiovascular pressure associated with mechanical contraction of the heart.

Electrodes 40, 44 and 48 may take the form of ring electrodes, and electrodes 42, 46 and 50 may take the form of extendable helix tip electrodes mounted retractably within insulative electrode heads 52, 54 and 56, respectively. Each of the electrodes 40, 42, 44, 46, 48 and 50 may be electrically coupled to a respective one of the coiled conductors within the lead body of its associated lead 18, 20, 22, and thereby coupled to respective ones of the electrical contacts on the proximal end of leads 18, 20 and 22.

Electrodes 40, 42, 44, 46, 48 and 50 may sense electrical signals attendant to the depolarization and repolarization of heart 12. The electrical signals are conducted to IMD 16 via the respective leads 18, 20, 22. In some examples, IMD 16 also delivers pacing pulses via electrodes 40, 42, 44, 46, 48 and 50 to cause depolarization of cardiac tissue of heart 12. In some examples, as illustrated in FIG. 2, IMD 16 includes one or more housing electrodes, such as housing electrode 58, which may be formed integrally with an outer surface of hermetically-sealed housing 60 of IMD 16 or otherwise coupled to housing 60. In some examples, housing electrode 58 is defined by an uninsulated portion of an outward facing portion of housing 60 of IMD 16. Other division between insulated and uninsulated portions of housing 60 may be employed to define two or more housing electrodes. In some examples, housing electrode 58 comprises substantially all of housing 60. Any of the electrodes 40, 42, 44, 46, 48 and 50 may be used for unipolar sensing or pacing in combination with housing electrode 58.

As described in further detail with reference to FIG. 4, housing 60 may enclose a stimulation generator that generates cardiac pacing pulses and defibrillation or cardioversion shocks, as well as a sensing module for monitoring the patient's heart rhythm.

Leads 18, 20, 22 also include elongated electrodes 62, 64, 66, respectively, which may take the form of a coil. IMD 16 may deliver defibrillation shocks to heart 12 via any combination of elongated electrodes 62, 64, 66, and housing electrode 58. Electrodes 58, 62, 64, 66 may also be used to deliver cardioversion pulses to heart 12. Electrodes 62, 64, 66 may be fabricated from any suitable electrically conductive material, such as, but not limited to, platinum, platinum alloy or other materials known to be usable in implantable defibrillation electrodes.

Pressure sensor 38 may be coupled to one or more coiled conductors within lead 18. In FIG. 2, pressure sensor 38 is located more distally on lead 18 than elongated electrode 62. In other examples, pressure sensor 38 may be positioned more proximally than elongated electrode 62, rather than distal to electrode 62. Further, pressure sensor 38 may be coupled to another one of the leads 20, 22 in other examples, or to a lead other than leads 18, 20, 22 carrying stimulation and sense electrodes. In addition, in some examples, pressure sensor 38 may be self-contained device that is implanted within heart 12, such as within the septum separating right ventricle 28 from left ventricle 32, or the septum separating right atrium 26 from left atrium 33. In such an example, pressure sensor 38 may wirelessly communicate with IMD 16.

The configuration of therapy system 10 illustrated in FIGS. 1 and 2 is merely one example. In other examples, a therapy system may include epicardial leads and/or patch electrodes instead of or in addition to the transvenous leads 18, 20, 22 illustrated in FIG. 1. Further, IMD 16 need not be implanted within patient 14. In examples in which IMD 16 is not implanted in patient 14, IMD 16 may deliver defibrillation shocks and other therapies to heart 12 via percutaneous leads that extend through the skin of patient 14 to a variety of positions within or outside of heart 12.

In other examples of therapy systems that provide electrical stimulation therapy to heart 12, a therapy system may include any suitable number of leads coupled to IMD 16, and each of the leads may extend to any location within or proximate to heart 12. For example, other examples of therapy systems may include three transvenous leads located as illustrated in FIGS. 1 and 2, and an additional lead located within or proximate to left atrium 33. As another example, other examples of therapy systems may include a single lead that extends from IMD 16 into right atrium 26 or right ventricle 28, or two leads that extend into a respective one of the right ventricle 26 and right atrium 28. An example of this type of therapy system is shown in FIG. 3.

FIG. 3 is a conceptual diagram illustrating another example of therapy system 70, which is similar to therapy system 10 of FIGS. 1-2, but includes two leads 18, 22, rather than three leads. Leads 18, 22 are implanted within right ventricle 28 and right atrium 26, respectively. Therapy system 70 shown in FIG. 3 may be useful for providing defibrillation and pacing pulses to heart 12.

FIG. 4 is a functional block diagram of one example configuration of IMD 16, which includes processor 80, memory 82, stimulation generator 84, sensing module 86, telemetry module 88, and power source 90. Memory 82 includes computer-readable instructions that, when executed by processor 80, cause IMD 16 and processor 80 to perform various functions attributed to IMD 16 and processor 80 herein. Memory 82 may include any volatile, non-volatile, magnetic, optical, or electrical media, such as a random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), electrically-erasable programmable ROM (EEPROM), flash memory, or any other digital media.

Processor 80 may include any one or more of a microprocessor, a controller, digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or equivalent discrete or integrated logic circuitry. In some examples, processor 80 may include multiple components, such as any combination of one or more microprocessors, one or more controllers, one or more DSPs, one or more ASICs, or one or more FPGAs, as well as other discrete or integrated logic circuitry. The functions attributed to processor 80 herein may be embodied as software, firmware, hardware or any combination thereof. Processor 80 controls stimulation generator 84 to deliver stimulation therapy to heart 12 according to a selected one or more of therapy programs, which may be stored in memory 82. Specifically, processor 44 may control stimulation generator 84 to deliver electrical pulses with the amplitudes, pulse widths, frequency, or electrode polarities specified by the selected one or more therapy programs.

Stimulation generator 84 is electrically coupled to electrodes 40, 42, 44, 46, 48, 50, 58, 62, 64, and 66, e.g., via conductors of the respective lead 18, 20, 22, or, in the case of housing electrode 58, via an electrical conductor disposed within housing 60 of IMD 16. Stimulation generator 84 is configured to generate and deliver electrical stimulation therapy to heart 12. For example, stimulation generator 84 may deliver defibrillation shocks to heart 12 via at least two electrodes 58, 62, 64, 66. Stimulation generator 84 may deliver pacing pulses via ring electrodes 40, 44, 48 coupled to leads 18, 20, and 22, respectively, and/or helical electrodes 42, 46, and 50 of leads 18, 20, and 22, respectively. In some examples, stimulation generator 84 delivers pacing, cardioversion, or defibrillation stimulation in the form of electrical pulses. In other examples, stimulation generator may deliver one or more of these types of stimulation in the form of other signals, such as sine waves, square waves, or other substantially continuous time signals.

Stimulation generator 84 may include a switch module and processor 80 may use the switch module to select, e.g., via a data/address bus, which of the available electrodes are used to deliver defibrillation shocks or pacing pulses. The switch module may include a switch array, switch matrix, multiplexer, or any other type of switching device suitable to selectively couple stimulation energy to selected electrodes.

Sensing module 86 monitors signals from at least one of electrodes 40, 42, 44, 46, 48, 50, 58, 62, 64 or 66 in order to monitor electrical activity of heart 12, e.g., via electrocardiogram (ECG) signals. Sensing module 86 may also include a switch module to select which of the available electrodes are used to sense the heart activity. In some examples, processor 80 may select the electrodes that function as sense electrodes via the switch module within sensing module 86, e.g., by providing signals via a data/address bus. In some examples, sensing module 86 includes one or more sensing channels, each of which may comprises an amplifier. In response to the signals from processor 80, the switch module of within sensing module 86 may couple the outputs from the selected electrodes to one of the sensing channels.

In some examples, one channel of sensing module 86 may include an R-wave amplifier that receives signals from electrodes 40 and 42, which are used for pacing and sensing in right ventricle 28 of heart 12. Another channel may include another R-wave amplifier that receives signals from electrodes 44 and 46, which are used for pacing and sensing proximate to left ventricle 32 of heart 12. In some examples, the R-wave amplifiers may take the form of an automatic gain controlled amplifier that provides an adjustable sensing threshold as a function of the measured R-wave amplitude of the heart rhythm.

In addition, in some examples, one channel of sensing module 86 may include a P-wave amplifier that receives signals from electrodes 48 and 50, which are used for pacing and sensing in right atrium 26 of heart 12. In some examples, the P-wave amplifier may take the form of an automatic gain controlled amplifier that provides an adjustable sensing threshold as a function of the measured P-wave amplitude of the heart rhythm. Examples of R-wave and P-wave amplifiers are described in U.S. Pat. No. 5,117,824 to Keimel et al., which issued on Jun. 2, 1992 and is entitled, “APPARATUS FOR MONITORING ELECTRICAL PHYSIOLOGIC SIGNALS,” and is incorporated herein by reference in its entirety. Other amplifiers may also be used. Furthermore, in some examples, one or more of the sensing channels of sensing module 86 may be selectively coupled to housing electrode 58, or elongated electrodes 62, 64, or 66, with or instead of one or more of electrodes 40, 42, 44, 46, 48 or 50, e.g., for unipolar sensing of R-waves or P-waves in any of chambers 26, 28, or 32 of heart 12.

In some examples, sensing module 86 includes a channel that comprises an amplifier with a relatively wider pass band than the R-wave or P-wave amplifiers. Signals from the selected sensing electrodes that are selected for coupling to this wide-band amplifier may be provided to a multiplexer, and thereafter converted to multi-bit digital signals by an analog-to-digital converter for storage in memory 82 as an electrogram (EGM). In some examples, the storage of such EGMs in memory 82 may be under the control of a direct memory access circuit. Processor 80 may employ digital signal analysis techniques to characterize the digitized signals stored in memory 82 to detect and classify the patient's heart rhythm from the electrical signals. Processor 80 may detect and classify the heart rhythm of patient 14 by employing any of the numerous signal processing methodologies known in the art.

If IMD 16 is configured to generate and deliver pacing pulses to heart 12, processor 80 may include pacer timing and control module, which may be embodied as hardware, firmware, software, or any combination thereof. The pacer timing and control module may comprise a dedicated hardware circuit, such as an ASIC, separate from other processor 80 components, such as a microprocessor, or a software module executed by a component of processor 80, which may be a microprocessor or ASIC. The pacer timing and control module may include programmable counters which control the basic time intervals associated with DDD, WI, DVI, VDD, AAI, DDI, DDDR, VVIR, DVIR, VDDR, AAIR, DDIR and other modes of single and dual chamber pacing. In the aforementioned pacing modes, “D” may indicate dual chamber, “V” may indicate a ventricle, “I” may indicate inhibited pacing (e.g., no pacing), and “A” may indicate an atrium. The first letter in the pacing mode may indicate the chamber that is paced, the second letter may indicate the chamber in which an electrical signal is sensed, and the third letter may indicate the chamber in which the response to sensing is provided.

Intervals defined by the pacer timing and control module within processor 80 may include atrial and ventricular pacing escape intervals, refractory periods during which sensed P-waves and R-waves are ineffective to restart timing of the escape intervals, and the pulse widths of the pacing pulses. As another example, the pace timing and control module may define a blanking period, and provide signals from sensing module 86 to blank one or more channels, e.g., amplifiers, for a period during and after delivery of electrical stimulation to heart 12. The durations of these intervals may be determined by processor 80 in response to stored data in memory 82. The pacer timing and control module of processor 80 may also determine the amplitude of the cardiac pacing pulses.

During pacing, escape interval counters within the pacer timing/control module of processor 80 may be reset upon sensing of R-waves and P-waves. Stimulation generator 84 may include pacer output circuits that are coupled, e.g., selectively by a switching module, to any combination of electrodes 40, 42, 44, 46, 48, 50, 58, 62, or 66 appropriate for delivery of a bipolar or unipolar pacing pulse to one of the chambers of heart 12. Processor 80 may reset the escape interval counters upon the generation of pacing pulses by stimulation generator 84, and thereby control the basic timing of cardiac pacing functions, including anti-tachyarrhythmia pacing.

The value of the count present in the escape interval counters when reset by sensed R-waves and P-waves may be used by processor 80 to measure the durations of R-R intervals, P-P intervals, P-R intervals and R-P intervals, which are measurements that may be stored in memory 82. Processor 80 may use the count in the interval counters to detect a tachyarrhythmia event, such as ventricular fibrillation event or ventricular tachycardia event. Upon detecting a threshold number of tachyarrhythmia events, processor 80 may identify the presence of a tachyarrhythmia episode, such as a ventricular fibrillation episode, a ventricular tachycardia episode, or a non-sustained tachycardia (NST) episode.

In some examples, processor 80 may operate as an interrupt driven device, and is responsive to interrupts from pacer timing and control module, where the interrupts may correspond to the occurrences of sensed P-waves and R-waves and the generation of cardiac pacing pulses. Any necessary mathematical calculations to be performed by processor 80 and any updating of the values or intervals controlled by the pacer timing and control module of processor 80 may take place following such interrupts. A portion of memory 82 may be configured as a plurality of recirculating buffers, capable of holding series of measured intervals, which may be analyzed by processor 80 in response to the occurrence of a pace or sense interrupt to determine whether the patient's heart 12 is presently exhibiting atrial or ventricular tachyarrhythmia.

In some examples, an arrhythmia detection method may include any suitable tachyarrhythmia detection algorithms. In one example, processor 80 may utilize all or a subset of the rule-based detection methods described in U.S. Pat. No. 5,545,186 to Olson et al., entitled, “PRIORITIZED RULE BASED METHOD AND APPARATUS FOR DIAGNOSIS AND GREATMENT OF ARRHYTHMIAS,” which issued on Aug. 13, 1996, or in U.S. Pat. No. 5,755,736 to Gillberg et al., entitled, “PRIORITIZED RULE BASED METHOD AND APPARATUS FOR DIAGNOSIS AND TREATMENT OF ARRHYTHMIAS,” which issued on May 26, 1998. U.S. Pat. No. 5,545,186 to Olson et al. and U.S. Pat. No. 5,755,736 to Gillberg et al. are incorporated herein by reference in their entireties. However, other arrhythmia detection methodologies may also be employed by processor 80 in other examples.

In the examples described herein, processor 80 may identify the presence of an atrial or ventricular tachyarrhythmia episode by detecting a series of tachyarrhythmia events (e.g., R-R or P-P intervals having a duration less than or equal to a threshold) of an average rate indicative of tachyarrhythmia or an unbroken series of short R-R or P-P intervals. The thresholds for determining the R-R or P-P interval that indicates a tachyarrhythmia event may be stored within memory 82 of IMD 16. In addition, the number of tachyarrhythmia events that are detected to confirm the presence of a tachyarrhythmia episode may be stored as a number of intervals to detect (NID) threshold value in memory 82. In some examples, processor 80 may also identify the presence of the tachyarrhythmia episode by detecting a variable coupling interval between the R-waves of the heart signal. For example, if the interval between successive tachyarrhythmia events varies by a particular percentage or the differences between the coupling intervals are higher than a given threshold over a predetermined number of successive cycles, processor 80 may determine that the tachyarrhythmia is present.

If processor 80 detects an atrial or ventricular tachyarrhythmia based on signals from sensing module 86, and an anti-tachyarrhythmia pacing regimen is desired, timing intervals for controlling the generation of anti-tachyarrhythmia pacing therapies by stimulation generator 84 may be loaded by processor 80 into the pacer timing and control module to control the operation of the escape interval counters therein and to define refractory periods during which detection of R-waves and P-waves is ineffective to restart the escape interval counters.

If IMD 16 is configured to generate and deliver defibrillation shocks to heart 12, stimulation generator 84 may include a high voltage charge circuit and a high voltage output circuit. In the event that generation of a cardioversion or defibrillation shock is required, processor 80 may employ the escape interval counter to control timing of such cardioversion and defibrillation shocks, as well as associated refractory periods. In response to the detection of atrial or ventricular fibrillation or tachyarrhythmia requiring a cardioversion pulse, processor 80 may activate a cardioversion/defibrillation control module, which may, like pacer timing and control module, be a hardware component of processor 80 and/or a firmware or software module executed by one or more hardware components of processor 80. The cardioversion/defibrillation control module may initiate charging of the high voltage capacitors of the high voltage charge circuit of stimulation generator 84 under control of a high voltage charging control line.

Processor 80 may monitor the voltage on the high voltage capacitor, e.g., via a voltage charging and potential (VCAP) line. In response to the voltage on the high voltage capacitor reaching a predetermined value set by processor 80, processor 80 may generate a logic signal that terminates charging. Thereafter, timing of the delivery of the defibrillation or cardioversion pulse by stimulation generator 84 is controlled by the cardioversion/defibrillation control module of processor 80. Following delivery of the fibrillation or tachycardia therapy, processor 80 may return stimulation generator 84 to a cardiac pacing function and await the next successive interrupt due to pacing or the occurrence of a sensed atrial or ventricular depolarization.

Stimulation generator 84 may deliver cardioversion or defibrillation shocks with the aid of an output circuit that determines whether a monophasic or biphasic pulse is delivered, whether housing electrode 58 serves as cathode or anode, and which electrodes are involved in delivery of the cardioversion or defibrillation shocks. Such functionality may be provided by one or more switches or a switching module of stimulation generator 84.

Telemetry module 88 includes any suitable hardware, firmware, software or any combination thereof for communicating with another device, such as programmer 24 (FIG. 1). Under the control of processor 80, telemetry module 88 may receive downlink telemetry from and send uplink telemetry to programmer 24 with the aid of an antenna, which may be internal and/or external. Processor 80 may provide the data to be uplinked to programmer 24 and the control signals for the telemetry circuit within telemetry module 88, e.g., via an address/data bus. In some examples, telemetry module 88 may provide received data to processor 80 via a multiplexer.

In some examples, processor 80 may transmit atrial and ventricular heart signals (e.g., electrocardiogram signals) produced by atrial and ventricular sense amp circuits within sensing module 86 to programmer 24. Programmer 24 may interrogate IMD 16 to receive the heart signals. Processor 80 may store heart signals within memory 82, and retrieve stored heart signals from memory 82. Processor 80 may also generate and store marker codes indicative of different cardiac episodes that sensing module 86 detects, and transmit the marker codes to programmer 24. An example pacemaker with marker-channel capability is described in U.S. Pat. No. 4,374,382 to Markowitz, entitled, “MARKER CHANNEL TELEMETRY SYSTEM FOR A MEDICAL DEVICE,” which issued on Feb. 15, 1983 and is incorporated herein by reference in its entirety.

The various components of IMD 16 are coupled to power source 90, which may include a rechargeable or non-rechargeable battery. A non-rechargeable battery may be selected to last for several years, while a rechargeable battery may be inductively charged from an external device, e.g., on a daily or weekly basis.

FIG. 5 is block diagram of an example programmer 24. As shown in FIG. 5, programmer 24 includes processor 100, memory 102, user interface 104, telemetry module 106, and power source 108. Programmer 24 may be a dedicated hardware device with dedicated software for programming of IMD 16. Alternatively, programmer 24 may be an off-the-shelf computing device running an application that enables programmer 24 to program IMD 16.

A user may use programmer 24 to select therapy programs (e.g., sets of stimulation parameters), generate new therapy programs, modify therapy programs through individual or global adjustments or transmit the new programs to a medical device, such as IMD 16 (FIG. 1). The clinician may interact with programmer 24 via user interface 104, which may include display to present graphical user interface to a user, and a keypad or another mechanism for receiving input from a user.

Processor 100 can take the form one or more microprocessors, DSPs, ASICs, FPGAs, programmable logic circuitry, or the like, and the functions attributed to processor 100 herein may be embodied as hardware, firmware, software or any combination thereof. Memory 102 may store instructions. For example, read only memory (ROM) stores computer instructions. Processor 80 is configured to access the computer instructions from ROM and then processor 80 executes the computer instructions. Execution of computer instructions by processor 80 can cause processor 100 to generate control signals to components of the IMD 16 or components electrically and/or mechanically coupled to IMD 16. Processor 80 can provide the functionality ascribed to programmer 24 herein, and information used by processor 100 to provide the functionality ascribed to programmer 24 herein. Memory 102 may include any fixed or removable magnetic, optical, or electrical media, such as RAM, ROM, CD-ROM, hard or floppy magnetic disks, EEPROM, or the like. Memory 102 may also include a removable memory portion that may be used to provide memory updates or increases in memory capacities. A removable memory may also allow patient data to be easily transferred to another computing device, or to be removed before programmer 24 is used to program therapy for another patient. Memory 102 may also store information that controls therapy delivery by IMD 16, such as stimulation parameter values.

Programmer 24 may communicate wirelessly with IMD 16, such as using RF communication or proximal inductive interaction. This wireless communication is possible through the use of telemetry module 102, which may be coupled to an internal antenna or an external antenna. An external antenna that is coupled to programmer 24 may correspond to the programming head that may be placed over heart 12, as described above with reference to FIG. 1. Telemetry module 102 may be similar to telemetry module 88 of IMD 16 (FIG. 4).

Telemetry module 102 may also be configured to communicate with another computing device via wireless communication techniques, or direct communication through a wired connection. Examples of local wireless communication techniques that may be employed to facilitate communication between programmer 24 and another computing device include RF communication according to the 802.11 or Bluetooth specification sets, infrared communication, e.g., according to the IrDA standard, or other standard or proprietary telemetry protocols. In this manner, other external devices may be capable of communicating with programmer 24 without needing to establish a secure wireless connection.

Power source 108 delivers operating power to the components of programmer 24. Power source 108 may include a battery and a power generation circuit to produce the operating power. In some embodiments, the battery may be rechargeable to allow extended operation. Recharging may be accomplished by electrically coupling power source 108 to a cradle or plug that is connected to an alternating current (AC) outlet. In addition or alternatively, recharging may be accomplished through proximal inductive interaction between an external charger and an inductive charging coil within programmer 24. In other embodiments, traditional batteries (e.g., nickel cadmium or lithium ion batteries) may be used. In addition, programmer 24 may be directly coupled to an alternating current outlet to power programmer 24. Power source 104 may include circuitry to monitor power remaining within a battery. In this manner, user interface 104 may provide a current battery level indicator or low battery level indicator when the battery needs to be replaced or recharged. In some cases, power source 108 may be capable of estimating the remaining time of operation using the current battery.

Referring again to FIG. 4, processor 80 of IMD 16 may detect a tachyarrhythmia episode, such as a ventricular fibrillation, ventricular tachycardia, fast ventricular tachyarrhythmia episode, or a NST episode, based on electrocardiographic activity of heart 12 that is monitored via sensing module 86. For example, sensing module 86, with the aid of at least some of the electrodes 40, 42, 44, 46, 48, 50, 58, 62, 64, and 66 (shown in FIGS. 1-2), may generate an electrocardiogram (ECG) or electrogram (EGM) signal that indicates the electrocardiographic activity. Alternatively, sensing module 86 may be coupled to sense electrodes that are separate from the stimulation electrodes that deliver electrical stimulation to heart 12 (shown in FIGS. 1-3), and may be coupled to one or more different leads than leads 18, 20, 22 (shown in FIGS. 1-2). The ECG signal may be indicative of the depolarization of heart 12.

For example, as previously described, in some examples, processor 80 may identify the presence of a tachyarrhythmia episode by detecting a threshold number of tachyarrhythmia events (e.g., R-R or P-P intervals having a duration less than or equal to a threshold). In some examples, processor 80 may also identify the presence of the tachyarrhythmia episode by detecting a variable coupling interval between the R-waves of the heart signal.

The techniques described in this disclosure, including those attributed to IMD 16, programmer 24, or various constituent components, may be implemented, at least in part, in hardware, software, firmware or any combination thereof. For example, various aspects of the techniques may be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuitry, as well as any combinations of such components, embodied in programmers, such as physician or patient programmers, stimulators, image processing devices or other devices. The term “processor” or “processing circuitry” may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry.

Such hardware, software, firmware may be implemented within the same device or within separate devices to support the various operations and functions described in this disclosure. In addition, any of the described units, modules or components may be implemented together or separately as discrete but interoperable logic devices. Depiction of different features as modules or units is intended to highlight different functional aspects and does not necessarily imply that such modules or units must be realized by separate hardware or software components. Rather, functionality associated with one or more modules or units may be performed by separate hardware or software components, or integrated within common or separate hardware or software components.

When implemented in software, the functionality ascribed to the systems, devices and techniques described in this disclosure may be embodied as instructions on a computer-readable medium such as RAM, ROM, NVRAM, EEPROM, FLASH memory, magnetic data storage media, optical data storage media, or the like. The instructions may be executed by one or more processors to support one or more aspects of the functionality described in this disclosure.

Presented in FIGS. 6-50 and the accompanying text is a series of operations performed on a wafer in order to form wafer to wafer interconnects as well as a hermetic seal to form a hermetic device. Table 1 presented below briefly summarizes each operation relative to each figure.

Referring to FIG. 6, a substrate 300, also referred to as a wafer, is obtained and placed in position to undergo multiple sequential processing operations some of which can be automated. The substrate 300 is typically comprised of a silicon crystal, commonly referred to as single crystal silicon or a glass composition. An exemplary glass composition can include borosilicate glass (BSG) commercially available from Plan Optik located in Elsoff, Germany. Substrate 300 includes a front side 302 a (first side or topside) and a backside 302 b (second side or bottom side). The back side 302 b is depicted horizontally along the x-axis while the top side 302 a is depicted vertically higher along the y-axis than back side 302 b and parallel to backside 302 b. The front and backsides 302 a,b undergo a series of operations in preparation for patterning of front and backsides 302 a,b.

Backside 302 b of the silicon substrate 300 is shown to have undergone a grinding and polishing operation so that the backside 302 b can receive a scribe, which identifies the wafer as being an individual wafer within a specific lot of wafers. Preferably, about Δy (y2−y1) which is about 1.5 mil of silicon is removed from backside 302 b during the grinding operation; however, skilled artisans appreciate that the amount of silicon removed can be adjusted. For example, an increased amount or decreased amount of silicon can be removed depending on the final desired characteristic of backside 302 b that undergoes the grinding operation. Grinding equipment manufactured by DISCO, located in Japan can be used to grind a portion of the silicon from backside 302 b.

After completion of the grinding operation, the substrate 300 is then loaded into a substrate mover, also referred to as a TEFLON® boat, so that the substrate can be moved into position for a cleaning operation. The substrate mover is configured to hold and move substrate 300 along an x-axis and/or a y-axis direction during the cleaning operation. For example, at operation 2, substrate 300 is placed in a substrate mover which is then positioned into cleaning equipment. The cleaning equipment includes a cleaning spray 301 in which compound(s) are sprayed onto the substrate 300 as shown in FIG. 7 while substrate 300 is rotated about the x-axis. The cleaning equipment is commercially available under the trade name Mercury from FSI equipment located in Chaska, Minn. Hydrogen peroxide (H₂O₂)/ammonium hydroxide (NH₄OH) and/or H₂O₂/hydrochloric acid (HCI) can be used as the cleaning spray 301 or as a part of the cleaning spray 301 for cleaning substrate 300. Substrate 300 is considered sufficiently cleaned once particulate matter, organic, ionic, and/or metallic impurities are removed from surfaces 302 a,b of substrate 300.

After the substrate 300 has been cleaned, barrier layers 308 a (or thermal oxide such as oxide, nitride, etc.) are formed on substrate 300 as shown in FIG. 8 in order to protect silicon 300 while a scribe is placed on the backside 302 b. It is appreciated that other barrier materials such as Silox, TEOS, silicon nitride, or various polyimides can be used. To form barrier layer 308 a, substrate 300 is placed into a substrate mover such as a silicon carbide boat which is configured to withstand high temperatures. The silicon carbide boat, carrying substrate 300, is pushed into a horizontal diffusion furnace while gases (oxygen O₂ (4 slm) and/or H₂) are introduced to the thermal processing chamber. The thermal processing chamber of a diffusion furnace is under atmospheric pressure and a temperature at about 1000° C. The diffusion furnace is commercially available from MRL Industries located in Sonora, Calif. After a portion of the silicon has been oxidized to form barrier layer 308 a, the gases (oxygen O₂ (4 slm) and/or H₂) are turned off and the silicon carbide boat is moved out of the thermal processing chamber. Barrier layer 308 a, also referred to as a thermal oxide layer, such as silicon dioxide, is formed over a top side 302 a and a backside 302 b of substrate 300 in order to protect the wafer while undergoing scribing at operation 4. As shown, barrier layer 308 a has a thickness of about 5,000 angstroms (Å). The barrier layer 308 a can range in thickness from about 4,000 Å to about 30,000 Å. In one or more embodiments, the thickness of the barrier layer 308 a is preferably about 15000 angstrom (Å).

At operation 4, the silicon substrate 300 receives a scribe 306 typically on the backside 302 b, as shown in FIG. 9. Scribing substrate 300 allows the wafer to be tracked through the remainder of the processing steps. A scribe 306 is preferably used on the backside 302 b to avoid particles and contaminants from collecting in the scribed area during, for example, a deposition step, thereafter spreading to other areas of the wafer during subsequent processing steps. Additionally, referring briefly to FIG. 45, since front side 402 of first substrate 300 a is bonded to front side 402 of second substrate 300 b, the only way to visually detect each scribe 306 is to ensure scribe 306 is placed on back side 302 b of each wafer.

At operation 5 shown in FIG. 10, barrier layer 308 is removed from substrate 300 through a stripping operation. To strip barrier layer 308 from substrate 300, the substrate 300 is placed into another substrate mover such as a TEFLON® boat. The TEFLON® boat securely holds and moves substrate 300 through a container of stripper until the barrier layer 308 is removed and silicon is exposed at the surface of the front and backsides 302 a,b. For example, the TEFLON® boat can be placed into a container of stripping solution such as hydrofluoric acid (HF) for about a minute to remove barrier layer 308.

At operation 6 shown in FIG. 11, the first and second sides 302 a,b of substrate 300 is cleaned through a wet chemical cleaning operation such as that which was previously described relative to operation 2. Cleaning spray 301 comprising H₂O₂/NH₄OH and/or H₂O₂/HCl is used to clean the first and second sides 302 a,b. Substrate 300 is then removed from the TEFLON® boat and placed into a silicon carbide mover or boat in preparation for moving the substrate 300 into the thermal processing chamber of the diffusion furnace.

At operation 7 shown in FIG. 12, first and second barrier layers 308 b (also referred to as thermal oxide layers) are formed on the first and second sides 302 a,b of substrate 300. First and second barrier layers 308 b are grown over first and second sides 302 a,b through a wet thermal oxidation process as previously described. Wet thermal oxidation is performed at, for example, 1200° C. for about three hours while O₂ and H₂ are continuously introduced into the thermal chamber of the diffusion furnace. As depicted in FIG. 12, barrier layer 308 b has a thickness of about 15,000 Å.

At operation 8, shown in FIG. 13, an excess amount of photoresist 310 a is introduced to or placed onto barrier layer 308 b. For example, a technique referred to as spin coating can be used to form a thin uniform layer of photoresist 310 a on the first side 302 a of substrate 300. Substrate 300 is secured inside a spin coater, which is then rotated at high speed in order to spread the fluid by centrifugal force. Rotation is continued while the excess photoresist 310 a spins off the edges of the substrate 300 and until the desired thickness of the film is achieved. The thickness of the photoresist 310 a can depend on the viscosity of the photoresist 310 a, the volatility of the photoresist 310 a, and/or the angular speed of spinning the substrate 300 in the spin coater. Photoresist 310 a thickness is nominally about 1.5 microns.

In this example, a positive photoresist 310 a is employed. An exemplary positive photoresist is commercially available as SPR3010 photoresist from Rohm and Hass located in Philadelphia, Pa. and now a wholly owned subsidiary of Dow Chemical Company.

At operation 9 shown in FIG. 14, a mask 312 a is placed and aligned over the positive photoresist 310 a. Mask 312 a, manually loaded into its fixture, includes continuous opaque areas that block or cover predetermined areas of the photoresist 310 a and apertures 314 that allow photoresist 310 a to be exposed to ultraviolet (UV) light 316 through a UV light aperture (not shown). UV light 316 contacts the photoresist 310 b which makes the photoresist 310 b soluble to an aqueous developer solution. An exemplary developer solution can be a MF26A developer, commercially available from Rohm and Hass. At operation 10 shown in FIG. 15, the developer solution (not shown) is introduced over the photoresist 310 b that was exposed to UV light 316. For example, the developer solution is spun onto the substrate 300 through the spin coating technique previously described. After the developer solution washes over the photoresist 310 a that was exposed to the UV light 316, the exposed photoresist 310 b is removed. Specifically, the exposed photoresist 310 b spins-off due to the centrifugal force applied to substrate 300 while substrate 300 continuously rotates about the y-axis, which is the vertical axis relative to the ground, in the spin coater. Substrate 300 is then moved to an etch processing chamber, referred to as a Rainbow model etcher, commercially available from Lam Research Corporation located in Fremont, Calif.

At operation 11 shown in FIG. 16, a portion of the barrier layer 308 is etched away through a plasma reactive ion etch (RIE) thereby forming a via 318. A via is a pad opening or recess. Via 318 is typically about 5 to 20 microns in diameter and possesses a height of about 0.1 to 1 micron. Dry etching involves applying or introducing plasma to the surface of substrate 300 such that the plasma strikes and etches the surface of substrate 300. Plasma includes reactive gases such as carbon tetrafluoride (CF₄) with the addition of ionized gasses such as nitrogen, argon, and/or helium or other suitable gases.

At operation 12 shown in FIG. 17, the remaining photoresist 310 b is stripped from the top surface 302 a of substrate 300 through the use of ionized oxygen plasma stripping operation until the exposed photoresist 310 b is removed. The oxygen plasma attacks and etches away the organic material (e.g. photoresist) but does not affect the inorganic material (e.g. silicon etc.). The stripper processing chamber, under a low pressure vacuum (e.g. 1.5 Torr), continuously removes etched volatilized particles away. The stripper processing chamber in stripping equipment is commercially available from Matrix located in Richmond, Calif. After the photoresist 310 b has been removed, via 318 is formed by first, and second surfaces 327 a-b, respectively.

Thereafter, substrate 300 is moved to the TEFLON® substrate 300 mover so that substrate 300 can undergo yet another cleaning operation. At operation 13 shown in FIG. 18, a wet chemical 317 is used to clean substrate 300 as similarly described relative to operations 2 and 6. Exemplary cleaning compounds for operation 13 include H₂O₂/NH₄OH and/or H₂O₂/HCI.

At operation 14 shown in FIG. 19, barrier layer 308 c is formed on the first and second sides 302 a,b of substrate 300, as previously described relative to operations 3 and 7 except the processing conditions are different. To illustrate, dry thermal oxidation is performed at, for example, 1,000° C. for about 30 minutes while O₂ and H₂ are continuously introduced into the thermal chamber of the diffusion furnace. Barrier layer 308 c,d is relatively thin and has a thickness of about 2,000 Å. Generally, barrier layer 308 c serves to increase the thickness of via layer 308 d.

Optional operations 15-19, shown in FIGS. 20-24, form vias 324, 314 in the backside 302 b of substrate 300 in order to form alignment features to align the first and the second wafers (also referred to as the first and second substrates 300 a, b, respectively) together prior to the bonding operation between the first and second wafers. At operation 15 shown in FIG. 20, a photoresist 310 c is applied through spin coating over the backside 302 b of substrate 300. An exemplary positive photoresist is commercially available as SPR3010 photoresist from Rohm and Hass located in Philadelphia, Pa. and a wholly owned subsidiary of Dow Chemical Company. Substrate 300 is positioned onto a hot plate upon which the substrate 300 is exposed to a short soft bake to harden the photoresist 310 c and drive out volatile components.

Soft baking can occur at a temperature of about 95 degrees Celsius for about 60 seconds. Soft-baking helps in photo-imaging and to remove any residual solvents from the photoresist 310 c.

At operation 16 shown in FIG. 21, a mask 312 b is placed over photoresist 310 c. Similar to operation 9, areas of the photoresist 310 c are exposed through the mask 312 b to allow UV light to pass through apertures in mask 312 b. At operation 17 shown in FIG. 22, a developer removes exposed photoresist 310 c through spinning of the substrate 300 in a spin coater. Vias 314, 324 are formed in photoresist 310 c after the exposed photoresist 310 c is removed. At operation 18 shown in FIG. 23, backside 302 b is dry etched in an Lam 4520 dry etcher. Plasma with carbon tetrafluoride (CF4) is used to etch thermal oxide 308 d. Plasma with nitrogen trifluoride (NF3) is used to etch thermal oxide 308 d. At operation 19 shown in FIG. 24, photoresist 310 c is removed from thermal oxide 308 d, through oxygen plasma RIE stripping operation as previously described.

At operation 20 shown in FIG. 25, conductive pad 320 (also referred to as conductive pad, solderable pad, or metal stack), comprises adhesion material, is formed through metal and/or alloy deposition. Metal and/or alloy deposition occurs in the via 318 and along the surface of thermal oxide 308 d. Adhesion material can be multilayered and comprise transition metal elements such as chromium and/or titanium (Ti) along with an optional barrier metal such as platinum (Pt) and/or nickel (Ni) and a wettable layer such as gold.

A wide variety of ways can be employed to deposit the metal or alloy into a via 318. Sputter deposition is an exemplary method that can be used. For example, a first conductive material 322 a such as Ti can be deposited into via 318. The first conductive material 322 a such as Ti can have a thickness of about 300 Å.

Thereafter, a second conductive material 322 b such as gold (Au) can be introduced or deposited over the first conductive material 322 a. The second conductive material 322 b such as Au can have a thickness of about 5,000 Å.

Typical metal stacks, formed by more than one layer of conductive material, can be Ti/Au/Ti (300/5000/300 Å) or Cr/Au/Ti (300/5000/300 Å) In one or more embodiments, an adhesion layer is always placed onto the barrier material 308 d. Typical adhesion layers can be Ti or Cr because gold does not adhere well to an underlying material. Thereafter, gold is placed over the adhesion layer. Finally, a Ti layer is placed on top of the second layer so that subsequent oxide layers will stick or adhere to the metal stack. Generally, oxide does not stick or adhere very well to Au. Thereafter, the top titanium layer is removed where the AuSn is desired to agglomerate but the Ti remains in areas that it is desirable for the oxide to continue to cover, as shown in the figures.

A third conductive material 322 c such as chromium (Cr) can be introduced over the second conductive material 322 b. For example, Cr can be deposited to a thickness of about 300 Å over the second conductive material 322 b. In one or more embodiments, Cr is deposited over the second conductive material 322 b through sputtering in which argon is employed. Sputter processes can occur over the wafer at temperatures up to 300° C. The vacuum chamber pressure is typically pumped to 1×10⁻⁷ Torr before sputtering begins, and during the processing of argon, pressure is typically 3 to 10 milliTorr. In one or more other embodiments, a thinner layer of second conductive material 322 b (e.g. gold etc.) can be formed. For example, the gold material can be about 1000 Å thick. In one or more other embodiments, first, second, and third conductive materials 322 a-c can comprise titanium, platinum, and titanium (Ti/Pt/Ti) material, respectively. In one or more embodiments, a preferable thickness is about 300 Å Ti, about 2000 Å Pt, and 300 Å Ti.

In one or more other embodiments, pad 320 (also referred to as conductive pad, solderable pad, or metal stack) can employ nickel vanadium (NiV)/Au/Ti as third conductive material 322 c, second conductive material 322 b, first conductive material 322 a, respectively.

In one or more other embodiments, it is appreciated that pad 320 can be formed of four or more conductive materials. For example, pad 320 can comprise Ti/Pt/Au/Ti in which fourth conductive material (not shown in FIG. 25) is Ti which is deposited on third conductive material 322 c. Third conductive material 322 c is Ni. Second conductive material 322 b is Au. First conductive material 322 a is Ti.

In one or more other embodiments, it is appreciated that pad 320 can be formed of four or more conductive materials. For example, pad 320 can comprise Ti/Ni/Au/Ti in which fourth conductive material (not shown in FIG. 25) is Ti which is deposited on third conductive material 322 c. Third conductive material 322 c is Ni. Second conductive material 322 b is Au. First conductive material 322 a is Ti.

At operation 21 shown in FIG. 26, photoresist 310 d is applied to third conductive metal 322 c using a spin coating operation. For example, positive photoresist is spun onto backside 302 b. An exemplary positive photoresist is commercially available as SPR3010 resist from Rohm and Hass.

A short soft bake is used to harden the photoresist 310 d and drive out volatile components from the photoresist. Soft baking can occur at a temperature of about 95° Celsius for about 60 seconds.

At operation 22 shown in FIG. 27, a mask 312 c partially covers photoresist 310 d. Photoresist 310 d is then exposed to UV light 316, thereby making the photoresist soluble to the developer solution. The UV light 316 contacts photoresist 310 d through an aperture(s) at a particular wavelength for that photoresist 310 d.

At operation 23 shown in FIG. 28, the photoresist 310 d that was exposed to the UV light 316 is then removed through the use of an aqueous developer. As previously described, the developer solution washes over the photoresist 310 d, which helps loosen the exposed photoresist 310 d from the third conductive metal 322 c.

At operation 24 shown in FIG. 29, the first, second, and third conductive material 322 a-c (e.g. Cr/Au/Ti metal) is etched. Chlorine gas is introduced into the reaction chamber of a Lam etcher and is subsequently ionized into a plasma. The plasma then etches the titanium. In contrast, a wet etching process is used to etch the first and second conductive metals 322 a,b. The wafer is placed in a TEFLON®boat, and is then placed in the wet etchant for that particular material being etched. For example, a wet etch potassium iodide (KI) and/or iodine (I₂) is used on the second conductive material 322 b. In particular, the wafer is placed into a container of the KI or I₂. After the second conductive material 322 b is sufficiently etched, the wafer is then rinsed in deionized water. The wafer is then moved to the next etching operation. For example, the wafer is then moved to etchant. A standard Cr etchant is used. For example, a chrome etch can comprise a mixture of ceric ammonium nitrate and nitric acid. An exemplary chrome etch is commercially available from Fujifilm Electronic Materials, North Kingstown, R.I.

At operation 25 shown in FIG. 30, the photoresist 310 d is removed from third conductive material 322 c through, for example, an oxygen plasma RIE stripping operation.

At operation 26 shown in FIG. 31, chemical vapor deposition (CVD) is used to deposit insulating material 326 (e.g. oxide, nitride etc.) over the barrier material 308 d and photoresist 310 d in order to create a barrier between, for example, second conductive material 322 b and a conductive material 340 (e.g. gold tin) subsequently used in forming the wafer to wafer interconnect. Insulating material 326 is located everywhere except in the via subsequently created in operation 30.

At operation 27 shown in FIG. 32, photoresist 310 e is applied to insulating material 326 (also referred to as barrier material). For example, a positive photoresist 310 e is spun onto topside 302 b using a spin coater. An exemplary positive photoresist is commercially available as SPR3010 photoresist from Rohm and Hass located in Philadelphia, Pa. A short soft bake is used to harden the photoresist 310 e and drive out volatile components. At operation 28 shown in FIG. 33, a mask 312 d is placed over photoresist 310 e, which allows a portion of the photoresist 310 e to be exposed to UV light 316 through the mask 312 d. Exposed photoresist 310 e is then soluble in the developer solution. At operation 29 shown in FIG. 34, exposed photoresist 310 e is removed through placing aqueous based developer over the exposed photoresist 310 e. At operation 30 shown in FIG. 35, insulating material 326 (e.g. oxide, nitride etc.) is etched away from the exposed area using plasma reactive ion that includes CF₄. At operation 31 shown in FIG. 36, the exposed photoresist 310 e is removed using oxygen plasma RIE strip. At operation 32 shown in FIG. 37, a portion of third conductive material 322 c, such as titanium, is removed from second conductive material 322 b through a plasma etching process in which the plasma includes chlorine.

At operation 33 shown in FIG. 38, a conductive material 340 a such as an alloy of gold tin (AuSn) (80%/20% by weight) is deposited at a typical thickness of 0.5 micron over the top surface of the insulating material 326 and a portion of the second conductive material 322 b (e.g. gold). Specifically, AuSn can be sputter deposited or electroplated at a thickness of about 5000 Å. In one or more other embodiments, a different thickness of AuSn can be used. In one or more embodiments, another alloy might be used such as AuSn 78%/22% can be used.

Operations 34-38 shown in FIGS. 39-43 relate to a lithographic process. At operation 34 shown in FIG. 39, photoresist 310 f is applied over conductive material 340 a. For example, a positive photoresist 310 f is spun onto conductive material 340 a. A short soft bake is used to harden the photoresist and drive out volatile components. At operation 35 shown in FIG. 40, a mask 312 e is placed over the photoresist 310 f, which allows a portion of the photoresist 310 f to be exposed to UV light through the mask 312 e. Exposed photoresist 310 f is then soluble in the developer solution. At operation 36 shown in FIG. 41, exposed photoresist 310 f is removed through placing aqueous based developer over the exposed photoresist 310 f. At operation 37 shown in FIG. 42, conductive material 340 a (e.g. AuSn) is etched away from the exposed area. For example, Sn can be etched away using a plasma etch of hydrogen bromide (HBr) while Au can be etched away using a wet etch KI or I₂. Residual tin can be further etched away using HBr plasma. An exemplary plasma etch tool is the Lam 9400 TCP etcher commercially available from Lam Research located in Freemont Calif.

At operation 38 shown in FIG. 43, the exposed photoresist 310 f is removed using oxygen plasma RIE strip followed by a conventional solvent resist stripping operation.

At operation 39 shown in FIG. 44, chemical mechanical polishing (CMP) is used to polish the top surface of insulative material 326, which is partially removed from a top surface of barrier material 308 d. After CMP is completed, a finished wafer 400 is formed. Finished wafer 400 has a frontside 402 (top side) and a bottom side 404. FIG. 44 shows details of one embodiment of a wafer before conductive material 340 a has undergone a reflow process. Reflow process implies that the finished wafers 400, 402 (also referred to as the first and second substrates) are exposed to heat until at least a portion of the first and second conductive material 340 a reflow and form an interconnect 340 b (also referred to as conductive pad).

FIG. 44 a shows details of one embodiment of a wafer after conductive material 340 a has undergone a reflow process to form a conductive pad 340 b

The relationship between the pad opening, AuSn diameter and AuSn thickness, and barrier material 308 d (e.g. glass) thickness can be shown relative to FIG. 83 and expressed as follows.

V_(total) = π r_(pad)²2H_(glass)B V_(1/2) = π r_(pad)²H_(glass)B = π r_(metal)²H_(metal) $\frac{r_{pad}}{r_{metal}} = \sqrt{\frac{H_{metal}}{{BH}_{Pad}}}$ V_(total):  total  solder  volume V_(1/2):  solder  volume  on  each  pad r_(pad):  radius  of  pad  opening r_(metal):  radius  of  AuSn  deposit H_(metal):  thickness  of  AuSn  deposit H_(glass):  thickness  of  top  glass B:  bulge  factor

The radius of the pad (r_(pad)) opening, (shown in third conductive material 322 c of FIG. 36) extends from the center of the conductive pad to the end of the second conductive material 322 c (e.g. Au or Pt), and r_(metal) extends from the center of the conductive pad to the end of the conductive material 340 a (e.g. AuSn). While the equations listed above can obtain a desirable AuSn volume, pad sizes and interconnect gap, other equations could also be written to express these relationships.

The height (H_(340a)) of the conductive material 340 a ranges from about 0.25 mircon to about 1.0 mircon. More, preferably, the H_(340a) has a height of 0.5 micron. When added to the height of conductive materials 322 a, 322 b, 322 c, and 326 H_(340a) must be, smaller than the height of the via (H_(via)) which is preferably 1.5 mircon. Referring to FIG. 44 a, the height of H1 is 1.5 micron whereas the height of H2 is 0.2 micron. Total height H_(total) is H1+H2, which equals 1.7 microns. H_(gap) is the height between H_(340a) (also referred to as H_(metal)) and the top surface 327 of barrier material 308 d. As shown in FIG. 43, conductive pad 340 c, after the reflow process, becomes substantially spherical, when reflowed without a mating substrate, and has a height of H_(pad) that is vertically higher than H_(340a). Preferably, H_(pad) ranges from about 0.5 microns to about 2 microns. Preferably, the H_(pad) has a height of 1.75 microns. Depending on the dewetting properties of the barrier material, the resulting shape may not be spherical but rather dome shaped. FIG. 41, for example, shown without a mating wafer, can produce a dome shaped interconnect between a first and second substrate after the reflow process.

At operation 40 shown in FIG. 45, a wafer to wafer bond (also referred to as a substrate 300 a to substrate 300 b bond) is formed in the wafer bonding chamber of a EVG 500 Series equipment commercially available from EV Group located in Tempe, Ariz.). The wafer bonding chamber is set at a temperature at about 200 degrees Celsius and operates at atmospheric pressure to form the wafer to wafer bond. Generally, formation of the wafer to wafer bond can take about 60 minutes to about 120 minutes.

The finished wafer 400 can be joined or bonded to another finished wafer 420, as shown by the wafer-to-wafer bond 500 in FIG. 45. In one embodiment, wafer 420 is a mirror image of wafer 400.

The face side 402 of finished wafer 400 is aligned and bonded to the face side 402 of finished wafer 420. Finished wafer 420 can be the same or different as finished wafer 400. For example, finished wafer 420 is different from finished wafer 400 in that finished wafer 402 lacks vias 314 b and 318. The first substrate 400 bonded to the second substrate 420 can be a glass to glass bond, glass-silicon bond, silicon-silicon bond, silicon to sapphire, sapphire to sapphire, and/or glass to sapphire. The glass to glass bond, glass-silicon bond, or silicon-silicon bond can be formed across an entire wafer with the exception of small recessed areas containing the pad structures

At operation 41 shown in FIG. 46, bonding begins to occur at an interface between facesides 402 of finished wafers 400, 402. The bond formed between finished wafers 400, 402 occurs at a temperature that is generally less than 250° C.

At operation 42 shown in FIG. 47, the conductive material 340 a (e.g. AuSn) undergoes a reflow process to form reflowed conductive material 340 b in a chamber of vacuum pressure furnace such as SST model 3130 is commercially available from SST International located in Downey, Calif. The conductive material 340 a can generally be reflowed at a temperature of about 305° C. and a N2 ambient. The pressure within the chamber is preferably standard atmospheric pressure. Conductive material 340 b solidifies after the temperature in the chamber begins to return to normal atmospheric temperature and/or pressure.

At operation 43 shown in FIG. 48, via 328, 330 are formed in substrate 300 through an etching process. For example, a wet etch can be used that comprises tetramethylammonium hydroxide (TMAH). Vias 328, 330 are formed in a substantially triangular shape or trench by the TMAH preferentially etching along a crystal lattice of the silicon. By etching along a crystal lattice of the silicon, a sloped via 328, 330 is achieved. At operation 44 shown in FIG. 49, the barrier material 308 d is stripped from substrate 300.

Table 1 presented below provides a brief description of the process operations used to form a wafer to wafer interconnect and/or seal as described in the text accompanying each figure.

TABLE 1 Brief summary of each operation Operation number Figure OPERATION 1 6 Grind backside of substrate 2 7 Clean substrate 3 8 Form barrier over the substrate 4 9 Scribe backside of the substrate 5 10 Remove barrier from the substrate 6 11 Clean substrate 7 12 Form thermal oxide over the substrate 8 13 Deposit photoresist over the thermal oxide 9 14 Place mask over the photoresist 10 15 Remove exposed photoresist 11 16 Dry etch thermal oxide 12 17 Remove remaining photoresist 13 18 Clean substrate 14 19 Form thermal oxide over the substrate 15 20 Apply photoresist to backside of the substrate 16 21 Place mask over the photoresist 17 22 Remove exposed photoresist 18 23 Dry etch backside of substrate to form vias 19 24 Remove resist 20 25 Form adhesion or barrier material over thermal oxide 21 26 Deposit photoresist over the barrier material 22 27 Place mask over photoresist 23 28 Remove exposed photoresist 24 29 Etch barrier material 25 30 Remove photoresist from barrier material 26 31 Deposit oxide over the barrier material 27 32 Deposit photoresist over the oxide material 28 33 Place mask over the photoresist 29 34 Remove exposed photoresist 30 35 Etch oxide 31 36 Remove photoresist 32 37 Remove titanium 33 38 Deposit conductive material to form a conductive pad 34 39 Apply photoresist to conductive material 35 40 Expose photoresist through mask 36 41 Remove exposed photoresist 37 42 Etch conductive material 38 43 Remove photoresist from conductive pad 39 44 Polish top surface 40 45 Couple the first and second substrates 41 46 Stabilize the bond 42 47 Reflow the conductive material in the conductive pad 43 48 Etch vias into the substrate 44 49 Remove thermal oxide

Table 2, presented below, provides experimental data as to the height, radii and volumetric measurements of the vias, and conductive pads. The measurements provided in Table 2 are in microns. For example, height and radii are in units of microns whereas volume is in cubic microns.

Wafer 4 Au Wafer 22 Pt Measured Measured H(pad) H(glass1) H(glass2) H(AuSn) r(pad) r(AuSn) V(AuSn) V(pad) H(metal_total) H(metal_total) 0.15 0.2 1.5 0.5 5 8 100.53 11.781 1.3 0.8 0.15 0.2 1.5 0.5 5 9 127.23 11.781 0.15 0.2 1.5 0.5 5 10 157.08 11.781 0.15 0.2 1.5 0.5 5 11 190.07 11.781 0.15 0.2 1.5 0.5 5 12 226.20 11.781 0.15 0.2 1.5 0.5 5 13 265.47 11.781 0.15 0.2 1.5 0.5 5 14 307.88 11.781 0.15 0.2 1.5 0.5 5 15 353.43 11.781 0.15 0.2 1.5 0.5 5 16 402.12 11.781 0.15 0.2 1.5 0.5 5 17 453.96 11.781 1.9 2.9

FIG. 50 is a flow diagram for forming a wafer to wafer interconnect and/or seal. At block 600, a first via is formed in a first side of a first substrate. At block 602, a first conductive pad is formed in the first via such that an exposed top surface of the first conductive pad is lower than a top surface of the first via. At block 604, a second via is formed in a first side of a second substrate. At block 606, a second conductive pad is formed in the second via such that an exposed top surface of the second conductive pad is lower than a top surface of the second via. At block 608, a reflow process forms the interconnect(s) and/or seal(s). The process disclosed herein significantly simplifies the polishing process. For example, the polishing process, discussed relative to the CMP description of operation 39, subjects only one material, oxide or nitride, to polishing. The CMP process of the present disclosure generally occurs without requiring the CMP to be applied to conductive material (e.g. metal, alloy). In contrast, the conventional approach typically requires CMP to be applied to oxide and metal. Additionally, the present disclosure also allows for electrical connections wherever electrical connections are needed and there is no need to add “dummy” connections. For example, to ensure CMP polish is evenly applied across the surface, the conventional process requires numerous conductive pads to be evenly distributed over the wafer surface. In essence, the extra conductive pads serve as a loading effect to facilitate the CMP but do not contribute to the electrical connections.

In one or more other embodiments, the conductive pad or solderable pad could be gold over titanium or gold over chromium. The underlying titanium or chromium layer(s) need only be thick enough to provide good adhesion. For example, titanium or chromium layer(s) should be in the 100s of Å. Preferably, the range of titanium should be about 100 Angstroms to about 500 Å. Preferably, the range of chromium is about 200 Angstroms to about 500 Å. Titanium would still be employed over the gold in areas covered with glass to improve the adhesion of the glass to the pad.

In yet another embodiment related to the solderable pad, gold could be replaced with platinum. The platinum pad is not consumed by the solder; therefore, the liquidus does not change due to the absorption of the gold. Preferably, the platinum thickness can range from about 100 to about 1000 Å thick. More preferably, the platinum thickness can range from about 100 to about 5000 Å thick. Using platinum in place of gold can be done for both the pad under the AuSn solder as well as a pad to which the AuSn might be joined during solder reflow process described herein.

Conductive pads or bumps can join in the middle of a via. In another embodiment, conductive pads or bumps can be located on one wafer making connection to pads on the mating wafer.

In one or more other embodiments, other metals such as palladium, copper, nickel, rhodium, tin, could be used in place of the gold in the solderable pads.

In one or more embodiments related to solderable pads (the Ti/Au/Ti or equivalent), rather than having the glass overlap the metal and define the conductive pad's 320 perimeter as shown in FIG. 51, the glass can be pulled back [and the pad 320 size and shape is defined by the patterning of the pad 320 itself as shown in FIG. 52. Pulled back refers to insulating material 326 (e.g. glass) as still being present but not laying on top of conductive materials 322, a,b, and c. In effect insulating material 326 becomes invisible and an integral part of barrier material 308 as depicted in FIG. 52.] The embodiment of FIG. 52 includes a pad 320, defined by pattern and etch processes, that will not wick Au/Sn under the glass as it dewets from the surrounding surface since there is no glass on top of conductive pad 320. Conductive pad 320 is made of conductive materials 322 b and 322 c. Conductive material 322 a is unnecessary since no adhesion layer is needed to make oxide 326 stick.

FIGS. 53-54 are a schematic view of yet another embodiment of a wafer to wafer interconnect. FIG. 53 depicts a bump to pad structure before a reflow process. As shown, one of the wafers 400 includes a conductive pad 346 that comprises two conductive materials 322 b,c. Conductive pad 322 bc could comprise less conductive materials than that which is shown. Conductive pad 322 bc extends horizontally over a via in conductive material 340 a but does not extend beyond the horizontal length of conductive material 340 a. In one or more other embodiments, Conductive pad 322 bc can be only slightly beyond the length of the contacting area of conductive material 340 a.

FIG. 54 shows the bump to pad structure after a reflow process has been completed. The wafer to wafer interconnect shown here can use any of the conductive materials described herein.

FIGS. 55-64 relate to one or more other embodiments that seal two wafers together through a wafer to wafer bond and subsequently form wafer to wafer interconnects and/or hermetic metal seals. FIG. 55 is a schematic view after a first and second sides 302 a,b of substrate 300 has undergone a cleaning operation such as the cleaning operation described relative to FIGS. 1-2. Referring to FIG. 56, thermal oxide 308 a is then formed over substrate 300 using, for example, the process described relative to operations 8-14 and shown relative to FIGS. 13-19. Thermal oxide 308 a,b can have a thickness, for example, of about 1.5 um.

FIG. 57 is a schematic view in which a via 318 is formed in thermal oxide 308 a. Via 318 can be formed through many different operations. Operations 15-19, described above, provide one way in which via 318 can be formed.

FIG. 58 is a schematic view of conductive metals deposited in via 318. A wide variety of ways can be employed to deposit the metal or alloy into via 318. For example, sputter deposition can be used. A first conductive material 322 a such as Cr can be sputter deposited into via 318. The first conductive material 322 a such as Cr can have a thickness of about 300 Å. Thereafter, a second conductive material 322 b such as Au or Pt can be introduced or deposited over the first conductive material 322 a. As shown in FIG. 58, the second conductive material 322 b, such as Au or Pt, can have a thickness of about 5,000 Å.

FIG. 59 depicts a metal pad 704 formed by etching a portion of the metal pad 704. Skilled artisans appreciate that while either a dry or wet etching process can be used to etch metal pad 704, the embodiment presented herein used a wet etchant e.g., potassium iodide followed by a dry etch with BCI₃. Metal pad 704 is formed of first and second conductive layers 322 a,b after a portion of conductive layers 322 a,b have been removed through etching.

As shown in FIG. 60, a third conductive material 702 such as AuSn can be introduced over the second conductive material 322 b. AuSn can be deposited (e.g. sputter deposited etc.) to a thickness of about 5000 Å over the second conductive material 322 b. In one or more embodiments, AuSn is deposited over the second conductive material 322 b through sputtering in which argon is employed. Sputter processes can occur over the wafer at temperatures up to 300° C. The vacuum chamber pressure is typically pumped to 1×10⁻⁷ Torr before sputtering begins, and during the processing of argon, pressure is typically 3 to 10 milliTorr. In one or more other embodiments, a thinner layer of second conductive material 322 b (e.g. gold, Pt, etc.) can be formed. For example, the gold or Pt can be about 1000 Å thick. In one or more other embodiments, first, second, and third conductive materials 322 a-b, 702 can comprise titanium, platinum, and AuSn (Ti/Pt/AuSn) material, respectively. In one or more other embodiments, first, second, and third conductive materials 322 a-b, 702 can comprise titanium, platinum, and AuSn (Ti/Au/AuSn) material, respectively. In one or more embodiments, a preferable thickness is about 300 Å Ti, about 5000 Å Au, and 300 Å Ti.

FIG. 61 depicts a schematic view in which a portion 718 of the third conductive metal 702 undergoes a removal process. Removal of the AuSn can be performed by numerous operations. For example, a photoresist material can be placed over the area in which removal of a portion 718 AuSn is desired. Thereafter, the photoresist along with the AuSn can undergo an etching process, as previously described. For example, Sn can be etched away using a plasma etch of hydrogen bromide (HBr) while Au can be etched away using a wet etch KI or I₂. Residual tin can be further etched away using HBr plasma.

After a portion 718 of the third conductive material 302 is removed, FIG. 62 shows a top surface of thermal oxide layers 308 a undergo a touch polish operation, as previously described.

FIG. 63 depicts a bump to bump structure 722 before undergoing a reflow process to form a low temperature bond between the two finished wafers 400, 420. FIG. 64 depicts a bump to bump structure 722 after undergoing a reflow process to form a wafer to wafer interconnect between the two finished wafers 400, 420. The reflow process conditions for reflowing bump to bump structure 722 involves using a chamber temperature of about 300 to about 310° C. for about 3 minutes to about 10 minutes. After undergoing a reflow process, a reflowed conductive material 724 is formed between a first and second finished wafers 400, 420

FIGS. 65-66 depicts a schematic view of yet another embodiment of a bump to mating metal pad structure 712 that form a low temperature bond between finished wafers 400, 420. Finished wafers 400 and 420 are formed in the same or similar manner as the finished wafers 400, 420 shown in FIGS. 56-64 except one of the finished wafers 400, 420 in FIGS. 65-66 includes mating metal pad 712 in place of first, second, and third conductive materials 322 a, 322 b, 702. In particular, one of the finished wafers 400 includes a front side 402 with AuSn that opposes a mating metal pad 712 on another finished wafer 420. The opposing, mating metal 712 can be any solderable metal, metal alloy, and/or a metal stack. A metal stack includes one or more metal layers operatively associated with an active device or passive device. The mating metal 712 can be Ti/Ni, Ti/Pt/Au, or Cr/Au, for example. Generally, the mating metal can be formed of a variety of thicknesses. For example, Ti/Ni can be about 250 Å/2000 Å, Ti/Pt/Au can be about 250 Å/500 Å/3000 Å, Cr/Au can be about 500 Å/4000 Å.

The bump to mating metal pad structure 712 undergoes a reflow process to form a low temperature interconnect of reflowed conductive material 726. The reflow process uses a temperature in the chamber of about 305° C. with an inert atmosphere. Generally, the reflow process can take about 3 to about 10 minutes. Generally, the mating metal 712 does not reflow. It simply wets the bump when it agglomerates on the opposing surface. After the reflow process, FIG. 66 depicts a bond 726 between finished wafers 400, 420.

FIGS. 67-78 relate to one or more other embodiments that seal two wafers together through a wafer to wafer bond. FIG. 67 is a schematic view after a first and second sides 302 a,b of substrate 300 has undergone a cleaning operation which allows thermal oxide 308 a to be formed thereover. An exemplary cleaning operation is described relative to FIGS. 1-2. Thermal oxide 308 a can be formed using, for example, the process described relative to operations 8-14 and shown relative to FIGS. 13-19. Thermal oxide 308 a,b have a thickness of about 15 k Angstroms.

FIG. 68 is a schematic view in which a via 318 is formed in barrier material 308 a. Via 318 can be formed through many different operations. Operations 15-19, described above, provide one way in which via 318 can be formed.

FIG. 69 depicts a thin layer (e.g. 2 k Angstroms) of barrier material or thermal oxide formed over barrier material 308 and into via 318.

FIG. 70 depicts multiple layers of conductive material 322 a-c deposited into the via 318 formed as shown in FIG. 68. A wide variety of ways can be employed to deposit the metal or alloy into via 318. For example, sputter deposition can be used. A first conductive material 322 a such as Cr can be sputter deposited into via 318. The first conductive material 322 a such as Cr can have a thickness of about 300 Å. Thereafter, a second conductive material 322 b such as Au or Pt can be introduced or deposited (e.g. sputter deposition etc.) over the first conductive material 322 a. The second conductive material 322 b, such as Au or Pt, can have a thickness of about 5,000 Å. The third conductive material 322 c is Ti which has a thickness up to or about 500 Å.

FIG. 71 depicts a portion of the first, second and third conductive materials 322 a-c removed from thermal oxide 308 a thereby leaving pad 804. A variety of ways can be used to remove a portion of the first, second and third conductive materials 322 a-c from the thermal oxide layer 308 a. FIGS. 26-30 and the accompanying text provide one way in which to remove a portion of the first, second and third conductive materials 322 a-c.

FIG. 72 depicts chemical vapor deposition of a barrier layer 342 comprising oxide or nitride over the remaining first, second and third conductive materials 322 a-c. In one or more embodiments, barrier layer 342 can possess a thickness of up to or about 3 k Å along the y-axis.

FIG. 73 depicts a portion of the barrier layer 342 removed thereby exposing a portion of third conductive material 322 c. A portion of the barrier layer 342 is etched away through a plasma reactive ion etch (RIE) thereby forming a via 344. Via 344 is typically about 5 to 20 microns in radius and possesses a height of about 0.1 to 1 micron. Dry etching involves applying or introducing plasma to the surface of barrier layer 342 such that the plasma strikes and etches the surface of barrier layer 342. Plasma includes reactive gases such as carbon tetrafluoride (CF₄) with the addition of ionized gasses such as nitrogen, argon, and/or helium or other suitable gases.

Any remaining photoresist (not shown) is stripped from the top surface of the barrier layer 342 through the use of ionized oxygen plasma stripping operation until the exposed photoresist is removed. The oxygen plasma attacks and etches away the organic material (e.g. photoresist) but does not affect the inorganic material (e.g. metal etc.). The stripper processing chamber, under a low pressure vacuum (e.g. 1.5 Torr), continuously removes etched volatilized particles away.

FIG. 74 depicts a portion of the third conductive layer 322 c (i.e. Ti) removed from a portion of the second conductive layer 322 b shown in FIG. 33. Third conductive layer 322 c can be removed through various lithographic processes.

Operations 34-38, shown in FIGS. 39-43, can be similarly applied in this embodiment to remove third conductive material 322 c (e.g. Ti) below the area in which barrier layer 342 was removed from FIG. 72. For example, Ti can be etched away using a plasma etch of hydrogen bromide (HBr) while Au can be etched away using a wet etch KI or I2. An exemplary plasma etch tool to etch Ti is the Lam 9400 TCP etcher commercially available from Lam Research located in Freemont Calif.

FIG. 75 depicts gold tin deposited over the structure depicted in FIG. 74. Fourth conductive material 322 d such as an alloy of gold tin (AuSn) (80%/20% by weight) is deposited at a thickness of about 0.5 micron over the top surface of the barrier material 342 and second conductive material (e.g. Au or Pt). Specifically, AuSn can be sputter deposited or electroplated at a thickness of about 5000 Å. In one or more other embodiments, a different thickness of AuSn can be used. In one or more embodiments, another alloy might be used such as AuSn 78%/22% can be used.

FIG. 76 depicts a portion of the gold tin removed from the structure depicted in FIG. 75. For example, Sn can be etched away using a plasma etch of hydrogen bromide (HBr) while Au can be etched away using a wet etch KI or 12. Residual tin can be further etched away using HBr plasma. FIG. 77 depicts the structure of FIG. 76 after it has undergone a light polishing operation through CMP.

FIG. 78 depicts a wafer to wafer bond between a first and second wafer 400, 420. Bonding begins to occur at an interface between facesides 402 of finished wafers 400, 402. The bond formed between finished wafers 400, 402 occurs at a temperature that is generally less than 250° C.

The conductive material 340 a (e.g. AuSn) undergoes a reflow process to form reflowed conductive material 340 b (FIG. 79) in a chamber of vacuum pressure furnace such as SST model 3130 is commercially available from SST International located in Downey, Calif. The conductive material 340 a can generally be reflowed at a temperature of about 305° C. and a N₂ ambient. The pressure within the chamber can be standard atmospheric pressure. Conductive material 340 b is formed after the temperature in the chamber begins to return to normal atmospheric temperature and//or pressure.

FIGS. 80-81 are the same as the embodiment 78-79 except one of the finished wafers 400 includes a mating metal pad 712, previously described instead of conductive material 340 a. After reflow, a wafer to wafer interconnect is shown in FIG. 81.

FIG. 82 depicts a single wafer 900 that uses the wafer to wafer bonding and interconnect technology described herein to form a seal ring. Conductive material (e.g. AuSn etc.) 908 is placed over thermal oxide 906. The substrate 902 can be silicon or borofloat 33 for example, with barrier material 904 disposed thereon. The active and passive circuits 910 are schematically designated. This single wafer 900 is subsequently wafer to wafer bonded to a mirror imaged wafer containing mirror imaged seal rings, then reflowed to create multiple hermetic metal seals. For implantable medical devices, copper is typically not used since copper lacks biostablity and will not provide an adequate seal in vivo.

FIG. 84 depicts SEMs of a reflowed dome shaped bump formed without the second substrate in order to demonstrate feasibility. The bump corresponds to the structure shown in FIG. 62 after the reflow process. As shown, there is no mating bump or pad. The pad that existed before the reflow process has de-wetted and agglomerated to a dome shape with a final height greater than the surrounding insulator 308 a.

Although various embodiments of the invention have been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to such illustrative embodiments. For example, it is to be appreciated that while specific examples of the processing equipment are provided, a variety of types of processing equipment can be used. Additionally, skilled artisans appreciate that while a positive photoresist was used in the process described herein, a negative photoresist could be used in place of the positive photoresist. If a negative photoresist is used, the mask should be configured to accommodate the negative photoresist.

Additionally, alternate processes and flows could be used to achieve the same end result. For example, a lift-off process rather than deposit, pattern and etch can be used to form the structures shown in FIG. 25 and FIG. 38-43. An exemplary lift off process may be seen with respect to U.S. Pat. No. 4,564,584, entitled PHOTORESIST LIFT-OFF PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES, issued to Fredericks et al on Jan. 14, 1986, the disclosure of which is incorporated by reference in its entirety herein.

Combining low temperature hermetic wafer bonding with an electrical interconnection is easier and cheaper to implement than conventional methods. For example, since each conductive pad is placed in a recessed cavity, the conductive pad does not interfere with CMP. Moreover, electrical connections can be provided in any location on the wafer since a solder bump is not placed on the surface of the wafer. Moreover, there is no need to add “dummy” connections merely to provide a uniform distribution of conductive pads across the wafer.

The present disclosure presents various embodiments for creating electrical interconnections between wafers using AuSn or other alloy deposited or otherwise applied to both opposing pads 320 to be connected. The present disclosure can also be applied to a bump-to-pad configuration, as shown in FIG. 53-54. Rather than two bumps coalescing as previously described, a single bump undergoes a reflow process and then makes contact with a solderable pad slightly below the surface of the mating wafer, as is shown in FIG. 54. It is also possible to apply the AuSn or other connection-forming alloy to just one of the surfaces, the other side being a pad 320, formed of to which the AuSn wets as it forms its near spherical shape during melting.

The bump-to-pad configuration can reduce cost by applying the AuSn to only one wafer rather than both. The bump-to-pad configuration also allows the pad-only wafer to be processed in a manner that might not be compatible with the wafer if the wafer had AuSn on the surface. For example oxygen plasma cleaning or oxidizing acids would oxidize the Sn in the AuSn and hinder a subsequent spherical or ball formation. This configuration however would not affect the wettability of a gold pad on a wafer.

The interconnect is accomplished the same way with the single-sided design as with the two-sided design previously disclosed. Wafers are brought together with pads aligned and the wafer stack is heated above the liquidus (280° C.) of the AuSn. The AuSn will dewet from the glass annulus around the wettable pad and attempt to form a sphere or dome shape to reduce surface energy. The AuSn volume is sufficient to cause the near-spherical AuSn to touch the wettable (most likely gold) pad on the opposing wafer and form the electrical contact. Again, no liquid or paste flux is used or is desired. This can be accomplished during or after the wafer bonding heat activation process.

The 80/20 weight percent AuSn alloy was described previously and is well-suited to this application because of its ability to be deposited, patterned and reflowed without flux. As mentioned previously, oxygen should be eliminated from the atmosphere to preclude oxidation during heating. Other alloys in the AuSn system such as AuSn 78/22 could prove beneficial. The additional Sn content allows the liquid AuSn to consume dissolved gold from the wettable pads without raising the liquidus temperature. This is evident from the AuSn binary phase diagram. AuSn 79/21 and other alloys are possible.

Other suitable alloys could include binary or higher-order combinations of Au, Sn, Ag, etc. Selection of an alloy with a desired liquidus temperature and wetting properties can provide preferable results. It is also understood that while Au is used in many embodiments, Pt can be substituted for Au.

The interconnect method described herein can be applied to any number of wafers properly aligned in a stack. Single and double-sided bonding could even be mixed within the stack. Single and double-sided bonding can be accomplished either serially by the addition of one or more wafers at a time to a previously processed subset of wafers or by processing the entire stack simultaneously.

As used herein, “have”, “having”, “include”, “including”, “comprise”, “comprising” or the like are used in their open ended sense, and generally mean “including, but not limited to”. It will be understood that “consisting essentially of”, “consisting of”, and the like are subsumed in “comprising” and the like. Accordingly, a first conductive material comprising titanium includes a first conductive material consisting essentially of, or consisting of, a titanium.

A variety of components can employ the technology described herein. Sensors (e.g. wireless sensors, leaded sensors), smart leads and/or miniature therapeutic devices exemplify the type of components that can implement the teachings of the present disclosure. The sensor, smart lead or miniature devices may or may not be protected and enclosed in an implantable cardioverter defibrillator (ICD) titanium can or housing. An example of a sensor may be seen with respect to U.S. Pat. No. 7,886,608 issued Feb. 15, 2011, and assigned to the assignee of the present invention, the disclosure of which is incorporated by reference in its entirety herein. An example of a biostable switch may be seen with respect to U.S. Pat. No. 7,388,459 issued Jun. 17, 2008, and assigned to the assignee of the present invention, the disclosure of which is incorporated by reference in its entirety herein. An example of an intravascular device may be seen with respect to U.S. Pregrant Publication 2007/0179552 to Dennis et al. published Aug. 2, 2007, US 2010/0305628 A1 to Lund Et al. and assigned to the assignee of the present invention, the disclosure of which are incorporated by reference in their entirety herein. An example of an implantable neurostimulator may be seen with respect to U.S. Pat. No. 7,809,443 issued Oct. 5, 2010, and assigned to the assignee of the present invention, the disclosure of which is incorporated by reference in its entirety herein. An example of an implantable agent delivery system may be seen with respect to U.S. Pregrant Publication No. 2010/0274221 A1 to Sigg. et al. published Oct. 28, 2010, and assigned to the assignee of the present invention, the disclosure of which is incorporated by reference in its entirety herein.

The description of the invention presented herein is merely exemplary in nature and, thus, variations that do not depart from the gist of the invention are intended to be within the scope of the invention. Variations are not to be regarded as a departure from the spirit and scope of the invention. 

1. A method for forming an integrated circuit comprising: providing a first substrate; forming a first conductive material that is entirely recessed relative to a surface of the first substrate; providing a second substrate; forming a second conductive material that is entirely recessed relative to a surface of the second substrate; and reflowing at least one of the first and second conductive material to form a single reflowed interconnect between the first and second substrate.
 2. The method of claim 1 wherein a hermetic seal is formed between the first and second substrate.
 3. The method of claim 1 wherein the single reflowed interconnect is an hour glass shape.
 4. The method of claim 1 wherein the first conductive material is a flowable pad which agglomerates toward a diametrically opposing pad.
 5. The method of claim 4 wherein the first conductive material is gold-tin (AuSn).
 6. The method of claim 4 wherein the second conductive material is one of a flowable pad and a nonflowable pad, the nonflowable pad does not reflow.
 7. The method of claim 1 wherein the first and second conductive materials are not copper.
 8. The method of claim 1 wherein the first substrate and the second substrate being one of silicon and glass, glass to glass, glass to silicon, silicon to silicon, silicon to sapphire, sapphire to sapphire, and glass to sapphire.
 9. The method of claim 5 wherein Au is present in an amount of about 80 weight percent and Sn is present in an amount of 20 weight percent of the AuSn.
 10. The method of claim 5 wherein Au is present in an amount of about 78 weight percent and Sn is present in an amount of 22 weight percent of the AuSn.
 11. The method of claim 5 wherein one of the first conductive pad and the second conductive pad comprising of palladium, copper, nickel, rhodium, tin, platinum, or gold.
 12. An implantable medical device made according to any of the claims 1-11.
 13. A pacing lead made according to any of the claims 1-11.
 14. A sensor made according to any of the claims 1-11.
 15. A communication device made according to any of the claims 1-11.
 16. A switch made according to any of the claims 1-11.
 17. A method comprising: providing a first substrate; introducing a first conductive material that is entirely recessed relative to a surface of the first substrate; providing a second substrate; introducing a second conductive material that is entirely recessed relative to a surface of the second substrate; and heating the first and second conductive material to form a single reflowed interconnect between the first and second substrate.
 18. The method of claim 17 further comprising forming an integrated circuit.
 19. The method of claim 18 wherein the integrated circuit is disposed in an implantable leadless pacemaker.
 20. The method of claim 18 wherein the integrated circuit is disposed in an implantable sensor.
 21. The method of claim 18 wherein the integrated circuit is disposed in an implantable communication device.
 22. The method of claim 18 wherein the integrated circuit is disposed in an implantable relay device.
 23. The method of claim 18 wherein the integrated circuit is disposed in a lead body.
 24. The method of claim 18 wherein the implantable medical device is a medical electrical lead with at least one integrated circuit disposed in a smart lead.
 25. An implantable medical device made according to any of the claim
 17. 26. An integrated circuit comprising: means for providing a first substrate; means for forming a first conductive material that is entirely recessed relative to a surface of the first substrate; means for providing a second substrate; means for forming a second conductive material that is entirely recessed relative to a surface of the second substrate; and means for reflowing at least one of the first and second conductive material to form a single reflowed interconnect between the first and second substrate.
 27. The method of claim 26 further comprising forming a hermetic seal between the first and second substrate.
 28. The method of claim 26 wherein the single reflowed interconnect is hour glass shaped and dome shaped.
 29. The method of claim 26 wherein the first conductive material is AuSn. 